Apparatus and method allocating virtual memory upon demand

ABSTRACT

An apparatus and method for allocating virtual memory upon demand to reduce the amount of virtual memory allocated. Privilege level transitions requested by a program of instructions invoke a fault handler routine which allocates memory for implementing the transition. Allocation of memory is thus delayed until such request for privilege level transition occurs.

FIELD OF THE INVENTION

The present invention relates, in general, to information handlingsystems and, in particular, to an apparatus and method for reducing theamount of virtual memory allocated to a program of instructions in aninformation handling system by allocating memory only upon demand.

BACKGROUND OF THE INVENTION

As computer environments become more and more complex, resources whichwere once taken for granted become a precious commodity. This is truetoday for virtual address space in the OS/2 operating system (OS/2 is atrademark of International Business Machines Corporation) environmentwhere more and larger application programs require significantquantities of memory. The operating system itself requires more storageto properly manage and protect these applications.

The architecture of the x86 series of processor by the Intel Corporation(on which OS/2 is based) provides four distinct privilege levels at thehardware level. These range from Ring 0, the most trusted privilegelevel, to Ring 3, or application privilege level (Ring 1 is currentlynot used by OS/2). Privilege levels are used to improve reliability ofthe operating system by protecting resources from direct access by lesstrusted entities. Each of these privilege levels require uniqueresources which are pre-allocated and stored away for subsequent useupon ring transition.

Under OS/2, the Ring 2 privilege level is used to provide theinput/output privilege level (IOPL), i.e. the privilege level or lowerprivilege levels in which code must be executing to be allowed by theIntel hardware to execute "sensitive" instructions. These sensitiveinstructions are typically used to manage physical devices and include,but are not limited to, I/O and interrupt servicing instructions, andare primarily useful for device-oriented situations where an applicationneeds to query device status. The Applicants have determined that thisability is not required by the majority of tasks which come and go in atypical operational environment. Therefore, as will be described in thespecification below, it is advantageous to delay the allocation ofresources required for the Ring 2 stack segment until such time as theyare actually required to reduce the amount of virtual memory allocated.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a method for reducingthe amount of memory allocated to a program of instructions implementedin an information handling system having one or more processors, memoryoperably associated with the processors, an operating system stored inthe memory, and a plurality of states in which instructions stored inthe memory are executed. The method comprises the step of allocatingmemory for initializing a first set of states and allocating memory forinitializing at least one selected state from the states when an attemptis made by one instruction or a set of instructions to transition to orfrom one of the states in the first set of states to or from theselected state.

The present invention is also directed to an information handling systemcomprising one or more processors, memory operably associated with theprocessors, an operating system stored in the memory, a plurality ofstates in which instructions stored in the memory are executed, andmeans for allocating memory for initializing a first set of the statesand means for allocating memory for initializing at least one selectedstate from the states when an attempt is made by one instruction or aset of instructions to transition to or from one of the states in thefirst set of states to or from the selected state.

The present invention is also directed to a computer program product forimplementing the above-described method.

The primary advantage of the present invention is the reduction of theamount of virtual memory allocated to a program of instructions.

Another advantage of the present invention is the allocation of virtualmemory only upon demand.

Another advantage of the present invention is greater efficiency ofvirtual memory use.

Another advantage of the present invention is the reduction in threadcreation time caused by not allocating virtual memory until needed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an information handling system embodying the presentinvention.

FIG. 2 is a flowchart depicting prior art stack allocations when athread is being created.

FIG. 3 is a flowchart illustrating stack allocations when a thread isbeing created according to the present invention.

FIG. 4 is a flowchart illustrating the steps implemented by a processorin making privilege level transitions from a first privilege level to asecond privilege level according to prior art.

FIG. 5 is a flowchart illustrating the steps performed by a processor inmaking a privilege level transition from a first privilege level to asecond privilege level according to the present invention.

FIG. 6 is a flowchart illustrating the process of FIG. 5 in greaterdetail by illustrating a fault handler according to the presentinvention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

Generally, the present invention provides an apparatus and method forreducing the amount of virtual memory allocated to a program ofinstructions.

In the following description, for purposes of explanation, specificprogram procedures, APIs, and configurations are set forth to provide athorough understanding of the present invention. The preferredembodiment described herein is implemented with an OS/2 operating systemcreated by IBM (IBM is a registered trademark of International BusinessMachines Corporation) and an Intel Corporation X86 seriesmicroprocessor. However, it will be apparent to one skilled in the artthat the present invention may be practiced without the specific detailsand be implemented in various computer systems having various processorsutilizing various operating systems and in various configurations ormakes or models of tightly coupled processors or in variousconfigurations of loosely coupled multiprocessor systems. The proceduraldescriptions and representations which follow are the means used bythose skilled in the art to convey the substance of their work to othersskilled in the art.

Referring now to FIG. 1, a representative hardware environment forpracticing the present invention is depicted and illustrates a typicalhardware configuration of a computer or information handling system inaccordance with the subject invention, having at least one centralprocessing unit (CPU) 10. CPU 10 is interconnected via system bus 12 torandom access memory (RAM) 14, read only memory (ROM) 16, andinput/output (I/O) adapter 18 for connecting peripheral devices such asdisc units 20 and tape drives 40 to bus 12, user interface adapter 22for connecting keyboard 24, mouse 26 having button 17, speaker 28,microphone 32, and/or other user interfaced devices such as a touchscreen device (not shown) to bus 12, communication adapter 34 forconnecting the information handling system to a data processing network,and display adapter 36 for connecting bus 12 to display device 38.

When an operating system prepares to begin the execution of a newthread, there are several initialization steps to be performed. One ofthe required steps is to allocate the stacks in virtual memory which thethreads will need or may need to use in order to run. Normally, theoperating system would allocate the stacks for each privilege level inwhich the thread could possibly execute. For OS/2, stacks would becreated for the privilege levels 0, 2, and 3. FIG. 2 illustrates thecreation of the stacks for privilege levels 2 and 3 in steps 100 and102, respectively. This figure shows that normally, when a thread isbeing created, a region of memory is reserved for the stack used whenthis thread is operating at privilege level 2. FIG. 3 furtherillustrates how step 100 is altered in the present invention. Instead ofallocating the stack for privilege level 2 as the thread is beingcreated, a specific value which indicates that the stack for privilegelevel 2 was not yet allocated is stored in a task state segment (TSS),thus deferring the allocation to a later time, if needed. Any thread orprocess that would require execution of any "sensitive" instructionwould require a transition to a privilege level less than or equal toIOPL. This class would encompass threads/processes that require devicecommunication or control. This can happen in the form of I/Oinstructions and interrupt servicing. This class would also includeinter-thread or inter-process interrupt serialization to maintain theintegrity of common data structures.

The dynamic nature of OS/2 does not allow knowing in advance the exactcode paths a program might take. Under certain conditions, dynamicallyloadable libraries (DLLS) that make transitions to the IOPL can beloaded, while under other circumstances the DLLs might not be loaded.Also, even if a DLL capable of executing an IOPL were to be loaded,there is no guarantee that a transition to the IOPL would necessarilyhave to occur.

By delaying the allocation right until the time it is actually requiredprovides the best way of insuring it is done only when needed. Theremainder of the steps necessary to prepare the thread for execution areunaltered, are well known in the art, and the details of such will notbe described as they are unnecessary for an understanding of the presentinvention.

Threads are created at privilege level 0, and once initialized, thethread begins to execute instructions while running at privilege level3. Depending on the specific code executing within the thread, aprivilege level transition could be requested. The transition could beto either privilege level 0 or 2. FIG. 4 depicts the role of the Intelprocessor as a thread running at privilege level 3 (see step 200) callscode which resides in another privilege level. Privilege leveltransitions from privilege level 3 to privilege level 0 or 2 occur as aresult of calling functions or APIs that reside in another privilegelevel, servicing an external interrupt, or handling a trap or fault (seesteps 202 and 204).

The Intel architecture provides a number of protected mode exceptions orsystem faults which are detected by hardware. An operating system hasthe ability to install full handlers for these exceptions or systemfaults which are allowed to resolve the faulting situation and resumeexecution at the faulting instruction. One of these restartable systemfaults or exceptions is issued when an invalid TSS is encountered. Thisdata structure is used during a ring transition to record the processorstate information. The TSS is defined by a descriptor which containsinformation including the limit, privilege level, and base address ofthe segment. The TSSes are allocated a stack of virtual memory space bythe operating system to record information for privilege leveltransitions.

The present invention also requires changes to the fault handlers thatget invoked when a called function or API results in a privilege leveltransition error. The actual processor calling mechanism is known as acall gate. The call gate is the method which initiates the hardwareprivilege level transition in the Intel processor. When the transitionis complete, the processor begins executing the called instructions atthe new privilege level (see step 206). When the function or API iscomplete, the hardware returns to the original privilege level of 3 (seestep 208) and continues executing code at that level (see step 210). Itwill be appreciated that in the preferred embodiment of the invention,there are no intermediate transition states between privilege levels,but such intermediate transition states may be possible.

Referring now to FIG. 5, a detailed flowchart illustrating the processwhich occurs in the hardware during a privilege level transition of acall gate is shown. There are many steps required to perform a privilegelevel transition. For complete details of this procedure, please referto the Intel Processor Family Developer's Manual. For example, the Intelprocessor executes microcode to perform privilege level transitions. Theflow chart of FIG. 5 focuses only on those steps necessary to describethe present invention.

As one of the steps performed during a call gate privilege leveltransition, the processor checks the stack selector value which isstored in the appropriate field for the target privilege level in theTSS to determine if the contents are valid (see step 300). It will beappreciated that any operating system running on Intel processors mustmake use of the TSS, and other non-Intel processors may implement a TSSor equivalent. Assuming the contents of the TSS are valid, theprocessor's stack selector, known as the SS register, gets loaded withthe value from the TSS (step 302). The same check is done for the targetprivilege level's stack pointer (step 304), and if valid, the SPregister is reloaded (step 306). Assuming both values are valid, thetransition is complete, and execution resumes at the address of thecalled function or API at the new privilege level. However, if the valuefor either the stack selector or the stack pointer is not valid, theprocessor generates a fault known as an Invalid TSS Exception, andcontrol is then passed to the exception or fault handler for that fault(steps 308 and 310). If the exception or fault handler was able tocorrect the faulting condition, the processor can then restart thefaulting instruction, and execution continues (step 312). If the faultis not correctable, a fatal error is generated (step 314).

The present invention takes advantage of the fact that the hardware inthe Intel processor will generate an Invalid TSS Exception if the targetprivilege level's stack selector is invalid. Since during the creationof the thread an invalid specific value was stored in the Ring 2 StackSelector value in the TSS, an Invalid TSS Exception will be generatedwhen this thread attempts to transition to Ring 2. FIG. 6 shows how theexception or fault handler for Invalid TSS faults is modified accordingto the present invention.

First, the Invalid TSS Exception or fault handler determines if thefault was caused by the invalid specific value stored in the TSS whenthe thread was created (step 400). If the fault was not caused by thisvalue, then the exception is processed according to current protocol ofOS/2 and Intel processor (see step 402). If the fault was caused by theinvalid specific value, then the following steps are performed: a regionof virtual memory is allocated for privilege level 2 stack (step 404),the fields in the TSS are updated with the actual stack selector andstack pointer values pointing to the newly allocated stack, theexception or fault handler is set to return to the faulting instructionfor restart, and the exception or fault handler process isterminated(step 406).

Next, control is returned to the Intel processor microcode for callgates, which control the privilege level transitioning, to test to seeif the fault is restartable (step 408 in FIG. 6 and step 312 in FIG. 5).If the fault is restartable, the hardware re-attempts to initiate theprivilege level transition and, this time finding valid values in theTSS fields, completes the transition.

This above description is, of course, a specific implementation of thepresent invention for the OS/2 operating system. However, the scope ofthe present invention is not specific to OS/2 or the Intel processor.The concept embodied in the present invention is to reduce theunnecessary consumption of critical system resources by allocating thoseresources just at the time they are actually needed, by the use ofrestartable operating system/hardware faults. The faults are used todetect an allocation requirement and to perform that requirement andmake the needed operating system management to allow the use of thatallocation. This reduces the demands on the operating system and limitsthe use of critical resources to only those aspects of the operatingsystem that are using them, rather than those that might use them. Itwill be appreciated that the present invention may be implemented in amultiple processor embodiment as well as a single processor embodiment.It will also be appreciated that the present invention may beimplemented in a non-threaded operating system, i.e. an operating systemwhich uses processes instead of threads.

Although the invention has been described with a certain degree ofparticularity, it should be recognized that elements thereof may bealtered by persons skilled in the art without departing from the spiritand scope of the invention. One of the embodiments of the invention canbe implemented as sets of instructions resident in the random accessmemory 14 of one or more computer systems configured generally asdescribed in FIG. 1. Until required by the computer system, the set ofinstructions may be stored in another computer readable memory, forexample in a hard disk drive, or in a removable memory such as anoptical disk for eventual use in a CD-ROM drive or a floppy disk foreventual use in a floppy disk drive. Further, the set of instructionscan be stored in the memory of another computer and transmitted over alocal area network or a wide area network, such as the Internet, whendesired by the user. One skilled in the art would appreciate that thephysical storage of the sets of instructions physically changes themedium upon which it is stored electrically, magnetically, or chemicallyso that the medium carries computer readable information. The inventionis limited only by the following claims and their equivalents.

What is claimed is:
 1. In an information handling system having one ormore processors, memory operably associated with the processors and anoperating system stored in the memory, a method for reducing the amountof memory allocated to an execution thread on said operating system,said method comprising the step of:upon initialization of said executionthread, allocating memory for storing at least a first set ofoperational data, said first set of operational data controllingoperational flow of said execution thread when said execution thread isexecuting in a first state; and upon transition of said execution threadto a second state, allocating memory for storing a second set ofoperational data, said second set of operational data controllingoperational flow when said execution thread is executing in said secondstate.
 2. The method, as recited in claim 1, wherein the memoryallocated in said steps of allocating memory is virtual memory.
 3. Themethod, as recited in claim 1, further comprising the stepsof:generating an exception when a fault instruction attempts totransition to or from said second state.
 4. The method, as recited inclaim 3, wherein said step of generating an exception includes the stepof executing a trap handler.
 5. The method, as recited in claim 4,wherein said trap handler executes the step of:allocating memory forinitializing said selected state.
 6. The method, as recited in claim 5,further including the steps of:clearing the exception; and re-executingthe fault instruction.
 7. The method, as recited in claim 4, whereinsaid trap handler is implemented by the operating system.
 8. The method,as recited in claim 1, wherein said first and second states areprivilege levels.
 9. An information handling system comprising:one ormore processors; memory operably associated with the processors; anoperating system stored in the memory; an execution thread on saidoperating system; means, upon initialization of said execution thread,for allocating memory for storing at least a first set of operationaldata, said first set of operational data controlling operational flowwhen said execution thread is executing in a first state; and means,upon transition of said execution thread to a second state, forallocating memory for storing a second set of operational data, saidsecond set of operational data controlling operational flow of saidexecution thread when said execution thread is executing in said secondstate.
 10. The information handling system, as recited in claim 9,wherein said means for allocating memory includes means for allocatingvirtual memory.
 11. The information handling system, as recited in claim9, further comprising:means for generating an exception when a faultinstruction attempts to transition to or from said second state.
 12. Theinformation handling system, as recited in claim 11, wherein said meansfor generating an exception includes a trap handler.
 13. The informationhandling system, as recited in claim 12, wherein said trap handlerincludes means for allocating memory for initializing said selectedstate.
 14. The information handling system, as recited in claim 13,further including:means for clearing said exception; and means forre-executing said fault instruction.
 15. The information handlingsystem, as recited in claim 12, wherein said trap handler is implementedby said operating system.
 16. The information handling system, asrecited in claim 9, wherein said first and second states are privilegelevels.
 17. A computer program product in a readable medium readable bya computer system for running an operating system including at least oneexecution thread, said computer system having one or more processors andmemory operably associated with the processors, said computer programproduct comprising:means, upon initialization of said execution thread,for allocating memory for storing at least a first set of operationaldata, said first set of operational data controlling operational flowwhen said execution thread is executing in a first state; and means,upon transition of said execution thread to a second state, forallocating memory for storing a second set of operational data, saidsecond set of operational data controlling operational flow when saidexecution thread is executing in said second state.
 18. The computerprogram product in a readable medium, as recited in claim 17, whereinsaid means for allocating memory includes means for allocating virtualmemory.
 19. The computer readable medium, as recited in claim 17,further comprising:means for generating an exception when a faultinstruction attempts to transition to or from said second state.
 20. Thecomputer program product in a readable medium, as recited in claim 19,wherein said means for generating an exception includes means forexecuting a trap handler.
 21. The computer program product in a readablemedium, as recited in claim 20, wherein said trap handler includes meansfor allocating memory for initializing said selected state.
 22. Thecomputer program product in a readable medium, as recited in claim 21,further comprising:means for clearing said exception; and means forre-executing said fault instruction.
 23. The computer program product ina readable medium, as recited in claim 20, wherein said trap handler isimplemented by said operating system.
 24. The computer readable medium,as recited in claim 17, wherein said first and second states areprivilege levels.